Design-Reuse

MIPI in FPGAs for mobile-influenced devices

A new wave of applications for mobile-influenced devices, using technology initially designed for mobile devices, demand high-resolution, high-frame-rate streaming data from vision sensors, especially ...
Business Wire

Mixel MIPI C-PHY/D-PHY Combo IP Integrated into Hercules Microelectronics HME-H3 FPGA

Mixel’s MIPI PHY IP integrated into the HME-H3 FPGA, the industry’s first FPGA to support MIPI C-PHY v2.0 SAN JOSE, Calif.--(BUSINESS WIRE)--Mixel ®, Inc. (Mixel), a leading provider of mixed-signal ...
Electronic Design

FPGA Bridges MIPI and More

Lattice Semiconductor’s CrossLinkPlus is designed to handle interface conversion, including support for MIPI virtual channels (Fig. 1). The chip will be useful to bridge between a peripheral’s ...
Business Wire

Mixel’s MIPI D-PHY IP Integrated into the Lattice CrossLink-NX FPGA

SAN JOSE, Calif.--(BUSINESS WIRE)--Mixel ®, a leading provider of mixed-signal intellectual property (IP), announced today that Mixel’s MIPI ® IP solution has been successfully integrated into Lattice ...
Design-Reuse

Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds

Arasan announces the immediate availability of its MIPI CSI IP supporting C-PHY v2.0 speeds of up to 54.72Gbps for FPGA designs November 14, 2022 -- San Jose, CA-- Arasan has released an all new ...
The Korea Herald

Arasan announces MIPI DSI IP for FPGA supporting full C-PHY 2.0 speeds

Arasan announces the immediate availability of its MIPI DSI IP supporting C-PHY v2.0 speeds of up to 54.72Gbps for FPGA designs SAN JOSE, Calif., Nov. 10, 2022 /PRNewswire/ -- Arasan has released an ...
The Korea Herald

Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds

Arasan announces the immediate availability of its MIPI CSI IP supporting C-PHY v2.0 speeds of up to 54.72Gbps (when operating up to 8 Gsps with all 3 channels) for FPGA designs SAN JOSE, Calif., Nov.